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this is information on a product in full production. may 2012 doc id 15450 rev 4 1/28 28 sthv748 quad 90 v, 2 a, 3/5 levels, high speed ultrasound pulser datasheet ? production data features 0 to 90 v output voltage up to 20 mhz operating frequency embedded low-power, floating high-voltage drivers (external voltage rails can be also used) mode operations: ? 3/5-levels output waveform ? 2 a source and sink current ?down 20 ps jitter ? anti-cross conduction function ?low 2 nd harmonic distortion fully integrated clamping-to-ground function ?8 synchronous active clamp ? anti-leakage on output node dedicated half bridge for continuous wave (cw) operations ? 0.1 w power consumption ? 0.6 a source and sink current ? 10 ps jitter fully integrated t/r switch ?13.5 on resistance ? hv mos topology to minimize current consumption ? up to 300 mhz bw ? receiver multiplexing function 2.4 v to 3.6 v cmos logic interface auxiliary integrated circuits ? noise blocking diodes ? fully self-biasing architecture ? anti-memory effect for all internal hv nodes ? thermal protection ? standby function latch-up free due to hv soi technology very few external passive components needed applications medical ultrasound imaging pulse waveform generator ndt ultrasound transmission piezoelectric transducers driver description this monolithic, high-voltage, high-speed pulser generator features four independent channels. it is designed for medical ultrasound imaging applications, but it can also be used for driving other piezoelectric, capacitive or mems based transducers. the sthv748 comprises a controller logic interface circuit, level translators, mosfet gate drivers, noise blocking diodes, and high-power p-channel and n-channel mosfets as the output stage for each channel, clamping- to-ground circuitry, anti-leakage, anti-memory effect block, thermal sensor, and a t/r switch which guarantees an effective decoupling during the transmission phase. moreover, the sthv748 includes self-biasing and thermal shutdown blocks. each channel can support up to five active output levels with two half bridges. the output stage of each channel is able to provide 2 a peak output current. in order to reduce power dissipation during continuous wave mode, a dedicated half bridge is available and the peak current is limited to 0.6 a. table 1. device summary order code package packaging STHV748QTR qfn64 tape and reel qfn64 9 x 9 x1.0 mm www.st.com
contents sthv748 2/28 doc id 15450 rev 4 contents 1 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 additional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 truth table and single channel block description . . . . . . . . . . . . . . . . . 8 4 power-up / power-down voltage sequence . . . . . . . . . . . . . . . . . . . . . . . 9 5 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 operating supply voltages and average currents . . . . . . . . . . . . . . . . 11 6.1 digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9 oscilloscope acquisitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
sthv748 typical application circuit doc id 15450 rev 4 3/28 1 typical application circuit figure 1. typical application circuit 7khupdo3urwhfwlrq &k$ 3bguy 3b gu y 3bguy 1bguy 1bguy 1bguy +956: orjlf ,1 ,1 ,1 ,1 7+6' '9'' +93 +93 +90 +90 '*1' 5()b+93 5()b+93 5()b+90 5()b+90 $*1' 67+9 +9287 ;'&5 /9287 +939 *1'b3:5 ,17b %,$6 fodps &s q) &q q) &s q) &q q) +939 +909 +909 7; 7; &: wr9 9''3 9''0 9 9 9 9wr9 gljlwdolqsxwv wr9 /1$ wr9 wr9 6hoi9rowdjh5hihuhqfh &k% &k & &k' o rj l f 'b&75 dqwlohdndjh dqwl phpru\ ; 9 53 . q 9 !-6
pin settings sthv748 4/28 doc id 15450 rev 4 2 pin settings 2.1 connection figure 2. pin connection (top view) 2.2 description 34(6 ). ).?" ).?" ).?" 6$$0 '.$?072 8$#2?" ,6/54?" ,6/54?# 8$#2?# '.$?072 6$$- ).?# ).?# ).?# 4(3$ !'.$ 2%& ?(6- (6-?# (6-?# (6/54 ?# (60 ?# 2%& ?(60 (60 ?# (60 ?$ 2%&?(60 (60 ?$ (6/54?$ (6-?$ (6-?$ 2%&?(6- $'.$ $6$$ ).4?")!3 ).?! ).?! ).?! 6$$- '.$?072 8$#2?! ,6/54?! ,6/54?$ 8$#2?$ '.$?072 6$$0 ).?$ ).?$ ).?$ !'.$ 2%&?(6- (6-?! (6-?! (6/54?! (60 ?! 2%& ?(60 (60?! (60 ?" 2%&?(60 (60?" (6/54?" (6-?" (6-?" 2%&?(6- $?#42 (66 table 2. pin description (p = power, a = analog, d = digital) pin n name function in/out type 1 agnd signal ground i a 2 ref_hvm1 supply for low side 1 gate driver i p 3 hvm1_a negative high-voltage supply 1 channel a i p 4 hvm0_a negative high-voltage supply 0 channel a i p 5hvout_a channel a, high-voltage output before noise blocking diodes op 6 hvp0_a positive high-voltage supply 0 channel a i p 7 ref_hvp1 supply for high side 1 gate driver i p 8 hvp1_a positive high-voltage supply 1 channel a i p 9 hvp1_b positive high-voltage supply 1 channel b i p 10 ref_hvp0 supply for high side 0 gate driver i p 11 hvp0_b positive high-voltage supply 0 channel b i p
sthv748 pin settings doc id 15450 rev 4 5/28 pin n name function in/out type 12 hvout_b channel b, high-voltage output before noise blocking diodes op 13 hvm0_b negative high-voltage supply 0 channel b i p 14 hvm1_b negative high-voltage supply 1 channel b i p 15 ref_hvm0 supply for low side 0 gate driver i p 16 d_ctr delay control i a 17 in4 input signal shared i d 18 in1_b input signal channel b i d 19 in2_b input signal channel b i d 20 in3_b input signal channel b i d 21 vddp positive low-voltage supply i a 22 gnd_pwr power ground i p 23 xdcr_b channel b, high-voltage output o p 24 lvout_b channel b, low-voltage output o a 25 lvout_c channel c, low-voltage output o a 26 xdcr_c channel c, high-voltage output o p 27 gnd_pwr power ground i p 28 vddm negative low-voltage supply i a 29 in3_c input signal channel c i d 30 in2_c input signal channel c i d 31 in1_c input signal channel c i d 32 thsd thermal shutdown pin i/o d 33 agnd signal ground i a 34 ref_hvm1 supply for low side 1 gate driver i p 35 hvm1_c negative high-voltage supply 1 channel c i p 36 hvm0_c negative high-voltage supply 0 channel c i p 37 hvout_c channel c, high-voltage output before noise blocking diodes op 38 hvp0_c positive high-voltage supply 0 channel c i p 39 ref_hvp1 supply for high side 1 gate driver i p 40 hvp1_c positive high-voltage supply 1 channel c i p 41 hvp1_d positive high-voltage supply 1 channel d i p 42 ref_hvp0 supply for high side 0 gate driver i p 43 hvp0_d positive high-voltage supply 0 channel d i p 44 hvout_d channel d, high-voltage output before noise blocking diodes op table 2. pin description (p = power, a = analog, d = digital) (continued)
pin settings sthv748 6/28 doc id 15450 rev 4 2.3 additional pin description the int_bias pin enables the internal reference generators. with int_bias=dvdd, the sthv748 internally generates the reference voltages on ref_hvp1/0 (pin - 7, 10, 39, 42) and ref_hvm1/0 (pin - 2, 15, 34, 47). these voltages are set at vddp below hvp and respectively at: ref_hvm# = hvm# + vddp ref_hvp# = hvp# - vddp after enabling int_bias, a period of time is needed to charge the external reference capacitors (about 30 s in a typical application). should int_bias=dgnd, it is necessary to apply an external voltage reference to the ref_hvm# and ref_hvp# pins. thsd is a thermal flag. being the output stage of the thsd a nch-mos open-drain, an external pull-up resist or (rp 10 k ) connected to a positive low-voltage supply (see figure 1 ) is required. if the internal temperature surpasses 153 c, thsd goes down and all sthv748 channels are in hz state. the thermal protection can be disabled, by connecting pin n name function in/out type 45 hvm0_d negative high-voltage supply 0 channel d i p 46 hvm1_d negative high-voltage supply 1 channel d i p 47 ref_hvm0 supply for low side 0 gate driver i p 48 dgnd logic ground i a 49 dvdd positive logic supply i a 50 in1_d input signal channel d i d 51 in2_d input signal channel d i d 52 in3_d input signal channel d i d 53 vddp positive low-voltage supply i a 54 gnd_pwr power ground i p 55 xdcr_d channel d, high-voltage output o p 56 lvout_d channel d, low-voltage output o a 57 lvout_a channel a, low-voltage output o a 58 xdcr_a channel a, high-voltage output o p 59 gnd_pwr power ground i p 60 vddm negative low-voltage supply i a 61 in3_a input signal channel a i d 62 in2_a input signal channel a i d 63 in1_a input signal channel a i d 64 int_bias enable internal supply generators i d exposed-pad substrate i p table 2. pin description (p = power, a = analog, d = digital) (continued)
sthv748 pin settings doc id 15450 rev 4 7/28 the thsd pin to a positive low voltage supply. thsd can be also shared among several sthv748 on the same pcb. d_ctr can be used to optimize 2 nd hd performances by tuning the fall propagation delay (tdf - see ta b l e 9 ). if d_ctr is equal to ground, tdf has the nominal value. if d_ctr is varied from 2 v to 4.2 v, tdf can be changed from -1 ns to +600 ps with respect to the nominal value. the exposed-pad is internally connected to the substrate of the package. it can be either left floating or connected to a ground via 100 v capacitance toward ground, in order to reduce the noise during the receiving phase. figure 3. typical application with int_bias shorted to ground. 7khupdo3urwhfwlrq &k$ 3bguy 3b guy 3bguy 1bguy 1bguy 1bguy +956: orjlf ,1 ,1 ,1 ,1 7+6' '9'' +93 +93 +90 +90 '*1' 5()b+93 5()b+93 5()b+90 5()b+90 $*1' 67+9 +9287 ;'&5 /9287 +939 *1'b3:5 ,17b%,$6 fodps 9h[whuqdoyrowdjhuhihuhqfh 9h[whuqdoyrowdjhuhihuhqfh &s &q &s &q +939 +909 +909 7; 7; &: wr9 9''3 9''0 9 9 9 9wr9 gljlwdolqsxwv wr9 /1$ wr9 wr9 6hoi9rowdjh5hihuhqfh &k% &k& &k' o r j l f 'b&75 dqwlo hd ndjh dqwl phpru\ ; 9 5 3 9h[whuqdoyrowdjhuhihuhqfh 9h[whuqdoyrowdjhuhihuhqfh !-6
truth table and single channel block description sthv748 8/28 doc id 15450 rev 4 3 truth table and single channel block description figure 4. single channel block description table 3. truth table for one channel global per channel state switches internal state thsd in4 in3 in2 in1 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 1 x x 0 0 clamp 0000001010 1 0 0 0 1 hvm0 0100000010 1 0 0 1 0 hvp0 1000000010 1 x 0 1 1 t/r sw 0000001101 1 0 1 0 1 hvm1 0001000010 1 0 1 1 0 hvp1 0010000010 1 0 1 1 1 hz 0000000010 1 1 1 1 1 t/r sw 0000001101 1 1 0 0 1max. hvm0 and hvm10101000010 1 1 0 1 0 max. hvp0 and hvp11010000010 1 1 1 0 1 cw hvm1 0000010010 1 1 1 1 0 cw hvp1 0000100010 0 x x x x hz 0000000010 +90 +93 +90 +93 *1'b3:5 3 1 3 1 3&: 1&: &/$03 *1'b3 :5 7 5 b6 ,* 1 $ / 756: +9287 /9 287 ;'&5 7khupdo vhqvrub 7khupdo vhqvrub 7rwkhupdosurwhfwl rq ,1 ,1 ,1 ,1 7+6' 3 1 3 1 3&: 1&: &/$03 756: 75b6,*1$/ /hyhovkliwhu jdwhgulyhu 3 1 3 1 h u p d o q v r u b 3 & : 1 & : k h u p d o hq v r u b & / $ / / 0 3 7 5 b 6 , * 1 $ / 7 5 6 : 7; 7; &: &o dps 1rl vh eor fnlq j glrg hv 75 vzlwfk 756: 6 6 6 6 6 6 6 6 6 6 !-v
sthv748 power-up / power-down voltage sequence doc id 15450 rev 4 9/28 4 power-up / power-down voltage sequence during the power up/power down phases,the following relationship must be always respected: vddp >= dvdd hvm0 <= hvm1 hvp0 >= hvp1 it is recommended to power up the low voltage supplies before the high voltage supplies.
electrical data sthv748 10/28 doc id 15450 rev 4 5 electrical data 5.1 absolute maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 4. absolute maximum ratings symbol parameter value unit agnd analog ground reference (1) 0v dgnd digital ground -300 to 300 mv gnd_pwr power ground -1.2 to 1.2 v vddp positive supply voltage -0.3 to 3.9 v vddm negative supply voltage 0.3 to -3.9 v dvdd positive logic voltage -0.3 to vddp v hvp0 tx0 high-voltage positive supply 95 v hvp1 tx1 high-voltage positive supply 0 to hvp0 v hvm0 tx0 high-voltage negative supply -95 v hvm1 tx1 high-voltage negative supply 0 to hvm0 v ref_hvp# high-voltage positive gate supply -0.3 < hvp - ref_hvp < 3.6 v ref_hvm# high-voltage negative gate supply -0.3 < ref_hvm - hvm < 3.6 v xdcr high-voltage output -95 to 95 v hvout high-voltage output before noise blocking diodes -95 to 95 v lvout low-voltage output -1 to 1 v dig i/o digital input specified in ta bl e 2 -0.3 to dvdd + 0.3 v d_ctr delay control -0.3 to 4.6 v t op operating temperature range -40 to 125 c t stg storage temperature range -65 to 150 c 1. agnd is the ground reference for all the other voltages. table 5. thermal data symbol parameter value unit r th,ja thermal resistance junction-ambient 30 (1) 1. this value is given for a two layer pcb (2s2p) and it?s strongly sensitive to pcb layout. increasing the number of pcb layers and/or adding heat sinks vi as , the thermal resistance value decreases. c/w
sthv748 operating supply voltages and average currents doc id 15450 rev 4 11/28 6 operating supply voltages and average currents operation conditions, unless otherwise specified, only one channel on, no load, hv=90 v, tx0 and tx1 on, int_bias=dvdd, dvdd=3 v, vddp=3 v and vddm=-3 v 6.1 digital inputs table 6. supply voltages and average currents symbol parameter conditions min. typ. max. units vddp positive supply voltage 2.7 3 3.6 v i vddp positive supply current pw mode (1) 1.5 ma i vddp_q standby mode (2) 1.1 ma vddm negative supply voltage -2.7 -3 -3.6 v i vddm negative supply current pw mode -1.5 ma i vddm_q standby mode -800 a dvdd positive logic voltage 2.4 3 min(3.6,v ddp+0.3) v i _dvd logic supply current pw mode 100 a i _dvd_q standby mode 85 a hvp high-voltage positive supply 0 90 v i hvp hv positive supply current pw mode 1 ma i hvp_q standby mode 350 a hvm high-voltage negative supply -90 0 v i hvm hv negative supply current pw mode -1 ma i hvm_q standby mode -350 a hvp-ref_hvp high-voltage positive gate supply 2.7 3 3.6 v ref_hvm-hvm high-voltage negative gate supply 2.7 3 3.6 v d_ctr delay control 0 4.2 v 1. in pw pulse wave mode the av erage current is measured over t _w time (see figure 6 ). 2. in standby mode all channels are in hz and int_bias= agnd" table 7. digital inputs symbol parameter min. max. units in1_#, in2_#, in3_#, in4, int_bias, thsd input logic high-voltage 0.8 dvdd dvdd v in1_#, in2_#, in3_#, in4, int_bias, thsd input logic low-voltage 0 0.2 dvdd v
operating supply voltages and average currents sthv748 12/28 doc id 15450 rev 4 6.2 output signals table 8. output signals symbol parameter min. max. units hvout high-voltage output before noise blocking diodes -90 90 v xdcr high-voltage output -90 90 v lvout low-voltage output -1 1 v thsd thermal shutdown pin 0 3 v
sthv748 electrical characteristics doc id 15450 rev 4 13/28 7 electrical characteristics table 9. static electrical characteristics (1) symbol parameter condition min. typ. max. units i n saturation current s1 - s3 hvp# =10 v, hvm# =-10 v, hvout=0 v 1.1 1.30 a hvp# =25 v, hvm# =-25 v, hvout=0 v 1.70 a hvp# =90 v, hvm# =-90 v, hvout=0 v 2a i p saturation current s0 - s2 hvp# =10 v, hvm# =-10 v, hvout=0 v 11.30 a hvp# =25 v, hvm# =-25 v, hvout=0 v 1.70 a hvp# =90 v, hvm# =-90 v, hvout=0 v 2a i ncw saturation current s5 hvp1=10 v, hvm1=-10 v, hvout=0 v 300 350 ma i pcw saturation current s4 hvp1=10 v, hvm1=-10 v, hvout=0 v 390 480 ma i cl saturation current s6 hvout=25 v 1.5 a r on_clamp on resistance s6 hvout=1 v 8 i l output leakage current, per channel h v p # = 9 0 v, h v m # = - 9 0 v, hvout=0 v 1 a h v p # = 9 0 v, h v m # = - 9 0 v, hvout=-90 v 1 h v p # = 9 0 v, h v m # = - 9 0 v, hvout=+90 v 1 p sb power dissipation in standby mode h v p # = 9 0 v, h v m # = - 9 0 v, hvout=0 v, int_bias=dgnd 4 w h v p # = 9 0 v, h v m # = - 9 0 v, hvout=0 v 126 150 mw p rx power dissipation in hvr_sw state h v p # = 3 0 v, h v m # = - 3 0 v, int_bias =0, all channels in receiving phase 30 mw v refp hvp# - ref_hvp# h v p # = 1 0 v, h v m # = - 1 0 v, hvout=0 v 0.8 vddp 1.2 vddp v v refn ref_hvm# - hvm# h v p # = 1 0 v, h v m # = - 1 0 v, hvout=0 v 0.8 vddp 1.2 vddp v t otp (2) overtemperature threshold hvp# =10 v, hvm# =-10 v 130 153 160 c t hys otp hysteresis hvp# =10 v, hvm# =-10 v 40 c
electrical characteristics sthv748 14/28 doc id 15450 rev 4 c t/r sw t/r sw capacitance lvout=0 v 40 pf r t/r sw_on t/r sw on resistance hvp# =10 v, hvm# =-10 v, xdcr=0 v, lvout=0.2 v 13.5 15.5 r t/r sw_off t/r sw off resistance hvp# =10 v, hvm# =-10 v, xdcr=1 v, lvout=0 v 1g vdrop_c w voltage drop between hvp1 and xdcr hvp# =10v, hvm# =-10v, i sink_xdcr =50 ma 2.58 2.79 2.9 v voltage drop between xdcr and hvm1 hvp# =10v, hvm# =-10v, i source_xdcr =50 ma 2.58 2.86 2.9 v 1. operating conditions, unless otherwise specified, int_bias=dv dd, hvp# = 90 v, hvm# = -90 v, vddp = 3 v, vddm = - 3 v, dvdd = 3 v, troom = 25 c. 2. guaranteed by bench characterization. table 9. static electrical characteristics (1) (continued) symbol parameter condition min. typ. max. units table 10. ac electrical characteristics (1) symbol parameter test condition min. typ. max. units f maximum output frequency 16 mhz 50 pf//200 22 mhz f cw maximum output frequency cw hvp1 =5 v, hvm1 = -5 v, continuous wave mode 20 mhz f bw output frequency bw h v p 1 = 5 0 v, h v m 1 = - 5 0 v, continuous wave mode, 50 pf//200 10 mhz t j output jitter 20 ps, rms t j-cw cw output jitter h v p 1 = 1 0 v, h v m 1 = - 1 0 v, continuous wave mode 5ps, rms t f fall time 28 ns t r rise time 28 ns t dr rise propagation delay 24 ns t df fall propagation delay 24 ns t/r sw t/r sw turn-on / turn-off time 170 ns hd2 2 nd harmonic distortion 1 pulse f = 1.7 mhz -40 dbc 1 pulse f = 5 mhz -40 dbc 5 pulses f = 1.7 mhz -40 dbc 5 pulses f = 5 mhz -40 dbc hd2pc pulse cancellation f = 1.7 mhz original and inverted pulse -40 dbc f = 5 mhz original and inverted pulse -40 dbc
sthv748 electrical characteristics doc id 15450 rev 4 15/28 bvd burst voltage drop 1 st to 128 th pulse hvp1 = 10 v, h v m 1 = - 1 0 v 2% p d_cw power dissipation, all channels cw mode, f = 5 mhz, hvp1 = 5 v, hvm1 = -5 v, no load 390 mw power dissipation, one channel cw mode, f = 5 mhz, hvp1 = 5 v, hvm1 = -5 v 320 t/r sw spike t/r sw spike on xdcr and lvout 100 m v pp x ta l k cross talk between channels. ampl(2ch)/ampl(1ch), 50 pf//200 -40 db 1. operating conditions, unless other wise specified, hvp# = 90 v, hvm# = -90 v, vddp = 3 v, vddm = -3 v, dvdd = 3 v, v, int_bias = dvdd, (hvp-ref_hvp) = 3 v, (ref_hvm-hvm) = 3 v, xdcr load c = 300 pf//r = 100 , lvout load c = 20 pf//200 t room = 25 c. table 10. ac electrical characteristics (1) symbol parameter test condition min. typ. max. units
timings sthv748 16/28 doc id 15450 rev 4 8 timings figure 5. t r , t f , t dr , and t df descriptions figure 6. pw example 5 periods, hvp0 = 90 v, hvm0 = -90 v, t=200 ns, t_tx=1.2 s, t_w=200 s !-v ,1 ;'&5 +93 +90 7 gu 7 gi 7 u 7 i ,1 ,1 ;'&5 +93 +90 +90 +93 ,1 !-v ,1 ,1 ,1 ,1 ;'&5 +93 +90 7 wk shulrg 7bw[ wudqvplvvlrqshulrg 7bz (qwluhzdihirup fodps 7bk
sthv748 timings doc id 15450 rev 4 17/28 figure 7. pw and hd2 example (hvp0=80 v, hvm0=-80 v load 300 pf//100 ) figure 8. pc example, hvp0 = 90 v hvm0 = -90 v, t=200 ns, t_pos= t_neg=400 ns !-v ;'&5b 3& ))7zlqgrz 7 ,1 ,1 ,1 ,1 +93 +90 ;'&5 7bsrv 7bqhj 7bqhj
timings sthv748 18/28 doc id 15450 rev 4 figure 9. cw mode example, hvp1 = 5 v, hvm1 = 5 v, t = 200 ns, t_tx>1 ms figure 10. t/r sw signal equivalent circuit model !-v ,1 ,1 ,1 ,1 7 7bw[ 7bk xdcr agnd lvout r s =1 3 rp=100 k cp=40 pf r s /2 r s /2 cp rp am020067v1
sthv748 timings doc id 15450 rev 4 19/28 figure 11. t/r sw bandwidth
timings sthv748 20/28 doc id 15450 rev 4 figure 12. possible external connection for lvout outputs with t/r sw in multiplexing driving configuration 48 (62?37 8$#2?! ,6/54?! 48 8$#2?" ,6/54?" 48 8$#2?# ,6/54?# 48 8$#2?$ ,6/54?$ 3ingle28chain 34(6 #(?! #(?" #(?# #(?$ ,.! 4'# 0'! ,0 &ilter !$ # !&% %#(/3)'.!,t %#(/3)'.!,tat %#(/3)'.!,tat %#(/3)'.!,tat -58command t -58command tat -58command tat -58command tat (62?37 (62?37 (62?37 !-v
sthv748 oscilloscope acquisitions doc id 15450 rev 4 21/28 9 oscilloscope acquisitions figure 13. tx0 = 60 v positive-negative pulses and immediately after tx1 = 30 v positive-negative pulses, load 300 pf // 100 figure 14. five-levels hv output voltage
oscilloscope acquisitions sthv748 22/28 doc id 15450 rev 4 figure 15. cw operations at 6 mhz figure 16. cw operations at 9 mhz
sthv748 oscilloscope acquisitions doc id 15450 rev 4 23/28 figure 17. two positive and two negative ?short pulses? with 10 ns time width for inputs in#, hvp/n/0/1 = 90 v, load 300 pf // 100 .
package mechanical data sthv748 24/28 doc id 15450 rev 4 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. note: qfn64 used for sthv748 has d variation option. table 11. qfn64 9 x 9 x 1.0 mm 64 pitch 0.50 mechanical data dim min. typ. max. a 0.8 0.9 1 a1 0.02 0.05 a2 0.65 1 a3 0.2 b 0.18 0.25 0.3 d 8.85 9 9.15 d1 8.75 d2 see exposed pad variation e 8.85 9 9.15 e1 8.75 e2 see exposed pad variation e 0.5 l 0.35 0.4 0.45 p 0.6 k 12 ddd 0.08 table 12. exposed-pad variation variation 6d2 e2 min. typ. max. min. typ. max. a 4.1 4.25 4.4 4.1 4.25 4.4 b 4.55 4.7 4.85 4.55 4.7 4.85 c 6.95 7.1 7.25 6.95 7.1 7.25 d 7.15 7.3 7.45 7.15 7.3 7.45
sthv748 package mechanical data doc id 15450 rev 4 25/28 figure 18. qfn64 9 x 9 x 1.0 mm 64 pitch 0.50 drawing 3fw#
package mechanical data sthv748 26/28 doc id 15450 rev 4 figure 19. qfn64 9 x 9 x 1.0 mm 64 tape and reel information dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.196 ao 12.25 12.45 0482 0.490 bo 12.25 12.45 0482 0.490 ko 2.1 2.3 0.083 0.091 po 3.9 4.1 0.153 0.161 p 15.9 16.1 0.626 0.639 .
sthv748 revision history doc id 15450 rev 4 27/28 11 revision history table 13. document revision history date revision changes 20-jan-2010 1 initial release. 17-feb-2010 2 updated typo on coverpage. 09-nov-2011 3 updated table 6: supply voltages and average currents , table 9: static electrical characteristics and table 10: ac electrical characteristics . minor text changes. 11-may-2012 4 updated the entire table 6: supply voltages and average currents title included. updated title in figure 6: pw example 5 periods, hvp0 = 90 v, hvm0 = -90 v, t=200 ns, t_tx=1.2 s, t_w=200 s . minor text changes.
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